Setups
General information
Wirnet™ iBTS information
Wirnet™ iFemtoCell information
Wirnet™ iFemtoCell-evolution information
Wirnet™ iStation information
System management
Network management
LoRa Features
KerOS customization
Support and resources
Setups
General information
Wirnet™ iBTS information
Wirnet™ iFemtoCell information
Wirnet™ iFemtoCell-evolution information
Wirnet™ iStation information
System management
Network management
LoRa Features
KerOS customization
Support and resources
This is an old revision of the document!
Required packages / tools to build the HALv2:
build-essentialtaropkg-build
Please ensure that these files are in the $PATH.
opkg-build can be installed by using this one-liner:
wget -qO- https://git.yoctoproject.org/cgit/cgit.cgi/opkg-utils/plain/opkg-build | sudo tee /usr/local/bin/opkg-build && sudo chmod 755 /usr/local/bin/opkg-build
The KerOS toolchain also needs to be installed. Toolchain can be download in the resource page. Instruction to install the toolchain are available in the toolchain dedicated page.
To compile the HALv2, please use following commands:
tar xzf libloragw2-5.1.0-klk5.tar.gz cd libloragw2-5.1.0-klk5 source /opt/toolchains/lpbs/environment-setup-cortexa9hf-neon-poky-linux-gnueabi ./configure --host=arm-poky-linux-gnueabi --prefix=/user/libloragw2
This should show something similar to:
checking for... ... configure: creating ./config.status config.status: creating ... config.status: executing depfiles commands
Check that there are no errors. Then, compile the tools:
make make fpga # This is optional and generates the IPK required to upgrade the FPGA to v61. make utils # This is optional and generates the utilities tools package. make install # To use the library to compile another program, compile the sources with this command. It will install the library under /tmp/libloragw/.
make fpga command will generate the IPK required to upgrade the FPGA to v61 with the name libloragw2-fpga_5.1.0-klk5_klk_lpbs.ipk. Previous IPK packages for upgrading FPGA were named libloragw2.
This means that it will be considered a different package by the package manager, and as a result, both will remain installed in the system.
To upgrade FPGA, please use the dedicated package libloragw2_5.1.0-klk1_klk_lpbs.ipk available here.
The main modification in tools since HALv1 is the -d argument.
As this HAL is mainly designed to handle multiple RF chips, this optional argument allows specifying which SPI device to use.
Kerlink provides an automatic discovery script at startup to handle correctly plugged boards.
By default, if a WAN module is provided, LoRaLoc modules are mapped from slot 2.
So to use tools with this LoRaLoc module, please specify on tool's command-line -d /dev/slot/2/spidev0.
For example:
./pkt_logger -d /dev/slot/2/spidev0
Due to architecture, the configuration is quite more complex than HAL v1:
This configuration must include SX1301 channel config.
These channels can be configured through sx1301ar_conf_chan function.
Please note that this function takes as “channel number” the concatenation of chip number and channel. (see function description in sx1301ar_hal.h)
This configuration is mainly used to correct RSSI and TX power values.
Corresponding calibration values are set in Production by Kerlink and extracted during board startup in /tmp/calib_loraloc.json file.
Thanks to ad9361 transceiver chip. We are able to get ± 0.25 dBm precision on real TX power.
As a consequence, up to 32 power steps (tx_lut) are generated and calibrated in production.
The JSON configuration file has been improved to simplify software by using JSON tables.
Indeed:
SX1301_array_conf is now a table to support multiple boards.rf_chain_conf is a 2-object-sized table.SX1301_conf is a 2-object-sized table.tx_lut is a variable table (up to 32 objects).
Semtech provides a set of tools in order to process tests on hardware components.
FPGA_CID of the board in order to ask AES key to Semtech.
To compile the tools follow the previous instruction: Wirnet™ iBTS Semtech HALv2 v5.1.0-klk5 - Instructions.
Archive with compiled tools is directly available in the dedicated resource page.
scp libloragw2-utils_5.1.0-klk5_lpbs.tar.gz root@<iBTS_IP>:/user/user directory: tar -xf libloragw2-utils_5.1.0-klk5_lpbs.tar.gz root@klk-lpbs-050789:/user/libloragw2-utils_5.1.0-klk5 # ll drwxr-xr-x 2 root root 4.0K Jun 11 09:54 . drwxr-xr-x 6 root root 4.0K Jun 11 09:54 .. -rwxr-xr-x 1 root root 381.3K Feb 14 13:56 chip_id -rw-r--r-- 1 root root 3.0K Feb 14 13:56 config.json -rw-r--r-- 1 root root 1.6K Feb 14 13:56 config_calib_prod.json -rwxr-xr-x 1 root root 417.5K Feb 14 13:56 klk_spectral_scan -rwxr-xr-x 1 root root 167.5K Feb 14 13:56 lbt_test lrwxrwxrwx 1 root root 23 Jun 11 09:54 local.json -> /tmp/calib_loraloc.json -rwxr-xr-x 1 root root 383.0K Feb 14 13:56 loraloc_info -rwxr-xr-x 1 root root 547.7K Feb 14 13:56 pkt_logger -rwxr-xr-x 1 root root 3.2K Feb 14 13:56 rx_test.sh -rwxr-xr-x 1 root root 490.7K Feb 14 13:56 send_pkt -rwxr-xr-x 1 root root 387.9K Feb 14 13:56 spectral_scan -rwxr-xr-x 1 root root 510.4K Feb 14 13:56 tx_continuous
This software provides FPGA chip ID.
./chip_id -d <SPI bus location>| Parameter | Value | Type | Description |
|---|---|---|---|
| -d | /dev/slot/N/spidevY | <int> | SPI device address. N: slot number. Y:spidev number. |
| -h | NA | NA | Displays help menu. |
./chip_id -d /dev/slot/2/spidev0 INFO: SPI speed set to 1000000 Hz INFO: board MASTER CHIP ID (LSB): 0x28730715 CHIP ID (MSB): 0x00f1408a
This program is used to configure a concentrator based on the Semtech 'SX1301 array' architecture based on a JSON configuration file, and then record all the packets received in log files, indefinitely, until the user stops the program.
No filtering is done and all the packets received by the concentrator should appear in the log.
./pkt_logger -d <SPI bus location>.Ctrl+C.| Parameter | Value | Type | Description |
|---|---|---|---|
| -d | /dev/slot/N/spidevY | <int> | SPI device address. N: slot number. Y:spidev number. |
| -h | NA | NA | Displays help menu. |
./pkt_logger -d /dev/slot/2/spidev0 +++ Start of packet logger for 'SX1301 array' concentrator +++ SX1301 array library version string: 5.1.0-klk5 INFO: SPI speed set to 1000000 Hz INFO: found configuration file config.json INFO: parsing concentrator parameters for board #0 INFO: Master board INFO: board center frequency configured at 866500000 Hz INFO: board RX bandwidth configured at 7000000 Hz INFO: rf_chain 0: RSSI offset configured at -202.5, a=20, b=2925 INFO: rf_chain 1: RSSI offset configured at -202.5, a=20, b=2925 INFO: gateway AES-128 key is configured to ABCDEF0123456789ABCDEF0123456789 INFO: Calibration room temperature (Tref) set to 22 oC INFO: Calibration radio temperature code at [Tref] set to 77 INFO: 1 dsp on the board INFO: chip 0 enabled INFO: chip 0 center frequency configured at 868000000 Hz INFO: LoRa multi-SF channel 0x00 configured at 867100000 Hz, BW 125kHz, SF 7 to 12 INFO: LoRa multi-SF channel 0x01 configured at 867300000 Hz, BW 125kHz, SF 7 to 12 INFO: LoRa multi-SF channel 0x02 configured at 867500000 Hz, BW 125kHz, SF 7 to 12 INFO: LoRa multi-SF channel 0x03 configured at 867700000 Hz, BW 125kHz, SF 7 to 12 INFO: LoRa multi-SF channel 0x04 configured at 867900000 Hz, BW 125kHz, SF 7 to 12 INFO: LoRa multi-SF channel 0x05 configured at 868100000 Hz, BW 125kHz, SF 7 to 12 INFO: LoRa multi-SF channel 0x06 configured at 868300000 Hz, BW 125kHz, SF 7 to 12 INFO: LoRa multi-SF channel 0x07 configured at 868500000 Hz, BW 125kHz, SF 7 to 12 INFO: LoRa stand-alone channel 0x08 configured at 868300000 Hz, BW 250000 Hz, SF 7 INFO: FSK channel 0x09 configured at 868800000 Hz, BW 125000 Hz, bit rate 50000 INFO: chip 1 enabled INFO: chip 1 center frequency configured at 868000000 Hz INFO: LoRa multi-SF channel 0x10 configured at 867100000 Hz, BW 125kHz, SF 7 to 12 INFO: LoRa multi-SF channel 0x11 configured at 867300000 Hz, BW 125kHz, SF 7 to 12 INFO: LoRa multi-SF channel 0x12 configured at 867500000 Hz, BW 125kHz, SF 7 to 12 INFO: LoRa multi-SF channel 0x13 configured at 867700000 Hz, BW 125kHz, SF 7 to 12 INFO: LoRa multi-SF channel 0x14 configured at 867900000 Hz, BW 125kHz, SF 7 to 12 INFO: LoRa multi-SF channel 0x15 configured at 868100000 Hz, BW 125kHz, SF 7 to 12 INFO: LoRa multi-SF channel 0x16 configured at 868300000 Hz, BW 125kHz, SF 7 to 12 INFO: LoRa multi-SF channel 0x17 configured at 868500000 Hz, BW 125kHz, SF 7 to 12 INFO: LoRa stand-alone channel 0x18 configured at 868300000 Hz, BW 250000 Hz, SF 7 INFO: FSK channel 0x19 configured at 868800000 Hz, BW 125000 Hz, bit rate 50000 INFO: parsing gateway parameters INFO: gateway MAC address is configured to 00AEAEFFFE000000 Configuring radio... Configuring DSP... INFO: [BRD0] enabling chip 0 INFO: [BRD0] enabling chip 1 INFO: [BRD0] channel diversity table: { 1 1 1 1 1 1 1 1 1 1 } --> board 0 started INFO: concentrator started INFO: Now writing to log file pktlog_00AEAEFFFE000000_20180611T115451Z.csv INFO: log file will be rotated every 600 seconds
This software starts a scan from 863 MHz to 870 MHz by step of 0.2 MHz with 1024 samples by frequency scan. This will be recorded in an output file named “scan.csv”.
./klk_spectral_scan -d <Serial port to use> -l <SPI bus location>.| Parameter | Value | Type | Description |
|---|---|---|---|
| -d | /dev/slot/N/ttyACM | <int> | Serial port to use. N: slot number. |
| -l | /dev/slot/N/spidevY | <int> | SPI device address. N: slot number. Y:spidev number. |
| -f | fstart:fstep:fstop | <float>:<float>:<float> | Frequency values to run the test. |
| -h | NA | NA | Displays help menu (more options available) |
./klk_spectral_scan -d /dev/slot/2/ttyACM -l /dev/slot/2/spidev0 INFO: SPI speed set to 1000000 Hz I/ Start frequency: 863000000 Hz I/ Stop frequency: 870000000 Hz I/ Step frequency: 200000 Hz I/ RSSI samples: 1024 I/ Bandwidth: 200000 Hz I/ Bit rate: 600 bps I/ Radio: 0 I/ Serial port: /dev/slot/2/ttyACM I/ SPI device port: /dev/slot/2/spidev0 I/ Gecko version: 1.0.6.0 I/ Output filename: scan.csv
This software configures the FPGA for “Listen-Before-Talk” feature and continuously reads the LBT channels timestamps which indicate when was the last instant when the channel was free.
./lbt_test <Parameters>.Ctrl+C.| Parameter | Value | Type | Description |
|---|---|---|---|
| -c | 868.3 | <float> | Center frequency for the test. |
| -d | /dev/slot/N/spidevY | <int> | SPI device address. N: slot number. Y:spidev number. |
| -f | 868.3 | <float> | Selected frequency the test. |
| -n | 1 | <int> | Number of lbt channels enabled for the test. |
| -r | -80 | <int> | RSSI target. |
| -s | 128 | <int> | Scan time in ms for an lbt channel. |
| -h | NA | NA | Displays help menu. |
/lbt_test -d /dev/slot/2/spidev0 -c 867.1 -f 867.1 -n 1 -r -80 -s 128 INFO: Starting LoRa Gateway v2 LBT test INFO: SPI speed set to 1000000 Hz INFO: FPGA VERSION = 61 INFO: Number of LBT channels: 1 INFO: RSSI target: -80dBm INFO: Scan time: 0x0 INFO: LBT channel 00 frequency: 867.1 MHz ~~~~~~~~~~~~ TIMESTAMP = 7063284 TIMESTAMP_CH0 = 7063330
This software is used to send test packets with an 'SX1301 array' concentrator.
./send_pkt -d <SPI bus location>.Ctrl+C.| Parameter | Value | Type | Description |
|---|---|---|---|
| -d | /dev/slot/N/spidevY | <int> | SPI device address. N: slot number. Y:spidev number. |
| -a | 0 | <int> | RF chain (0 or 1). |
| -b | 125 | <int> | Bandwidth [125,250,500]. |
| -s | 7 | <int> | LoRa Spreading Factor [7-12] |
| -t | 1000 | <int> | Pause between packets (ms). |
| -p | 2 | <int> | RF power (dBm). |
| -f | 868.3 | <float> | Target frequency (MHz). |
| –rfreq | 868.5 | <float> | Radio RX central frequency. |
| -h | NA | NA | Displays help menu (more options available) |
./send_pkt -d /dev/slot/2/spidev0 -a 0 -b 125 -s 7 -t 1000 -p 2 -f 868.3 --rfreq 868.5 debug: 1, 868.300000, 1000, 0.000000 +++ Start of packet sender for 'SX1301 array' concentrator +++ SX1301 array library version string: 5.1.0-klk1 INFO: SPI speed set to 1000000 Hz Configuring radio... Configuring DSP... INFO: [BRD0] enabling chip 0 INFO: [BRD0] enabling chip 1 INFO: [BRD0] channel diversity table: { 0 0 0 0 0 0 0 0 0 0 } --> board 0 started INFO: concentrator started NOTE: emitting on 36 channel starting at @868.300MHz with 0.200MHz offset NOTE: Concentrator board configuration: Radio configuration: RX center freq 868500000 Hz, RX bandwidth 7000000 Hz non-LoRaWAN, or private network mode LoRa modulation, BW 125kHz, SF 7, CR 1, normal polarity +2dBm TX power, 32 bytes payload, default preamble length XX^C
This software is used to scan the spectral band where the Wirnet™ iBTS operates. It simply computes an RSSI histogram on several frequencies, that will help to detect occupied bands and get interferer profiles. It logs the histogram in a .csv file.
./spectral_scan -d <SPI bus location>.
| Parameter | Value | Type | Description |
|---|---|---|---|
| -d | /dev/slot/N/spidevY | <int> | SPI device address. N: slot number. Y:spidev number. |
| -f | fstart:fstep:fstop | <float>:<float>:<float> | Frequency values to run the test. |
| -l | scan.csv | <string> | File to store output data scan. |
| –rfreq | 868.3 | <int> | Radio RX central frequency. |
| -h | NA | NA | Displays help menu. |
./spectral_scan -d /dev/slot/2/spidev0 -f 867.1:0.2:868.5 +++ Start RSSI histogram of 'SX1301 array' channels +++ SX1301 array library version string: 5.1.0-klk5 INFO: SPI speed set to 1000000 Hz FPGA version: 61 File : rssi_histogram.csv Freq start : 867100000 Hz Freq stop : 868500000 Hz Freq step : 200000 Hz Pts per step: 8192 Rate : 12500 Hz RSSI offset : -143 dBm Radio RX center frequency: 866500000 Hz 867100000 10%<-137 30%<-128 50%<-125 80%<-120 867300000 10%<-137 30%<-128 50%<-125 80%<-120 867500000 10%<-137 30%<-128 50%<-125 80%<-120 867700000 10%<-137 30%<-129 50%<-125 80%<-121 867900000 10%<-137 30%<-129 50%<-125 80%<-121 868100000 10%<-138 30%<-129 50%<-125 80%<-121 868300000 10%<-138 30%<-129 50%<-125 80%<-122 868500000 10%<-140 30%<-131 50%<-128 80%<-123 INFO: SPI link closed +++ Exiting RSSI histogram program +++
This software is used to set Wirnet™ iBTS in Tx continuous mode, for spectral measurement. The user can set the modulation type, the modulation parameters, and the multiple gains of the Tx chain. The program runs indefinitely until the user stops the application.
./tx_continuous -d /dev/slot/2/spidev0.| Parameter | Value | Type | Description |
|---|---|---|---|
| -d | /dev/slot/N/spidevY | <int> | SPI device address. N: slot number. Y:spidev number. |
| -f | frequency | <float> | Selected frequency the test in MHz. |
| -h | NA | NA | Displays help menu (other options available) |
./tx_continuous -d /dev/slot/2/spidev0 -f 868.5 SX1301 array library version string: 5.1.0-klk5 RF frequency: 868.500 MHz (868500000 Hz) RF path: 0 Modulation: LORA SF:7 BW:125 kHz INFO: SPI speed set to 1000000 Hz TX Gains: FPGA:5 TX Gains: AD9361: Atten:87, AuxDAC Vref:3, AuxDAC:770 TX Gains: AD9361 Temperature Compensation: Tref_code: 77, coeff_a:0, coeff_b:0 Configuring radio... Configuring DSP... INFO: [BRD0] enabling chip 0 INFO: [BRD0] channel diversity table: { 0 0 0 0 0 0 0 0 0 0 } --> board 0 started INFO: final atten used with temperature compensation is 87 running... Enter "n<value>" to modify atten Enter "d<value>" to modify auxdac_word value Enter "a<value>" to modify temperature compensation coeff A Enter "b<value>" to modify temperature compensation coeff B Enter "q" to quit q INFO: concentrator stopped INFO: SPI link closed
This program is used to configure a concentrator based on the Semtech 'SX1301 array' architecture based on a JSON configuration file, and then record all the packets received in log files, indefinitely, until the user stops the program. Available configuration options are different from pkt_logger utility.
./rx_test.sh -d <SPI bus location>.Ctrl+C.| Parameter | Value | Type | Description |
|---|---|---|---|
| -d | /dev/slot/N/spidevY | <int> | SPI device address. N: slot number. Y:spidev number. |
| -h | NA | NA | Displays help menu. |
./rx_test.sh -d /dev/slot/2/spidev0 -f 868500000 -frx 868000000 -s 12 +++ Start of packet logger for 'SX1301 array' concentrator +++ SX1301 array library version string: 5.1.0-klk5 INFO: SPI speed set to 1000000 Hz INFO: found configuration file debug_conf.json INFO: parsing concentrator parameters for board #0 INFO: Master board INFO: board center frequency configured at 868000000 Hz INFO: board RX bandwidth configured at 7000000 Hz INFO: rf_chain 0: RSSI offset configured at -202.5, a=0, b=0 INFO: rf_chain 1: RSSI offset configured at -202.5, a=0, b=0 INFO: gateway AES-128 key is configured to ABCDEF0123456789ABCDEF0123456789 INFO: Calibration room temperature (Tref) set to 22 oC INFO: Calibration radio temperature code at [Tref] set to 77 INFO: 1 dsp on the board INFO: chip 0 enabled INFO: chip 0 center frequency configured at 868500000 Hz INFO: channel 0x00 disabled INFO: channel 0x01 disabled INFO: channel 0x02 disabled INFO: channel 0x03 disabled INFO: channel 0x04 disabled INFO: channel 0x05 disabled INFO: channel 0x06 disabled INFO: channel 0x07 disabled INFO: LoRa stand-alone channel 0x08 configured at 868500000 Hz, BW 125000 Hz, SF 12 INFO: FSK channel 0x09 configured at 868500000 Hz, BW 15600 Hz, bit rate 2400 INFO: chip 1 disabled INFO: parsing gateway parameters INFO: gateway MAC address is configured to 7276FF002E050789 Configuring radio... Configuring DSP... INFO: [BRD0] enabling chip 0 INFO: [BRD0] enabling chip 1 INFO: [BRD0] channel diversity table: { 0 0 0 0 0 0 0 0 0 0 } --> board 0 started INFO: concentrator started INFO: Now writing to log file pktlog_7276FF002E050789_20180612T095435Z.csv INFO: log file will be rotated every 864000 seconds ** Waiting for packets .... INFO: No fine timestamp available for matching Temp from AD9361 = 15 oC (69) "sys time (UTC)","GPS timestamp","board","counter timestamp","frequency","channel nb (ant0)","RSSI (ant0)","channel nb (ant1)","RSSI (ant1)","status","size","modulation","B W (kHz)","SF","data rate","CR","SNR (ant0)","SNR (ant1)","ftime (ant0)","ftime (ant1)","payload (hex)" RSSI= "RSSI (ant0)", SNR= "SNR (ant0)" "2018-06-12 09:57:54.895Z",,0,0199534630,868500000,8,-78,,,"CRC OK",23,"LoRa",125,12,,1,+9.0,,,,"00324652-4112B218-00B41D00-0000B218-0097E1B8-DA0CD2" RSSI= -78, SNR= +9.0 ^C root@klk-lpbs-050789:/user/libloragw2-utils_5.1.0-klk5 # Nb valid packets received: 1 CRC OK INFO: concentrator stopped INFO: SPI link closed INFO: log file closed, 1 packet(s) recorded +++ Exiting packet logger +++
This software is used to display hardware/software information.
./loraloc_info -d /dev/slot/2/spidev0.| Parameter | Value | Type | Description |
|---|---|---|---|
| -d | /dev/slot/N/spidevY | <int> | SPI device address. N: slot number. Y:spidev number. |
| -h | NA | NA | Displays help menu |
./loraloc_info d /dev/slot/2/spidev0 INFO: SPI speed set to 1000000 Hz fpga_cid = 0x00F1408A28730715 fpga_swver = 61 Sx1301_1_cid = 1 Sx1301_1_ver = 103 Sx1301_2_cid = 1 Sx1301_2_ver = 103 DSP_1 = OK DSP_2 = OK